1. Field of the Invention
The present invention relates to a semiconductor chip stack and manufacturing method thereof, and more particularly, to a semiconductor chip stack having through-silicon via (TSV) and manufacturing method thereof.
2. Description of the Prior Art
Integrated circuit (IC) products are constructed by chips that are fabricated by conventional semiconductor manufacturing processes. The processes to fabricate a chip start with a wafer: a plurality of regions is defined on a wafer. Then, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are performed to form the desired circuit trace(s) and followed by separating each region to form a plurality of chips. Chips are packaged to form a chip package; and the chip package is attached on a board such as a printed circuit board (PCB). It is also well-known that the chip is electrically connected to pins on the PCB and thus each of the programs on the chip can be performed.
Pursuing thinner and lighter IC products, the semiconductor industries always tries to reach the limits to the process miniaturization, and to develop different package technologies. For example, flip-chip (FC) technology, multi-chip package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology are developed to stack the chips or packages in three dimensions, therefore density of the semiconductor devices per unit volume is increased. In recent years, a “through-silicon via (TSV)” technique is further developed to improve interconnections between chips in the package so as to increase the package efficiency.
Please refer to FIGS. 1-2, which are schematic drawings of a conventional IC product. Left of FIG. 1 is a schematic drawing of a wafer; and right of FIG. 1 is an enlarged view of a region in the wafer of FIG. 1. As shown in FIG. 1, IC product is fabricated by providing a wafer 100 having a plurality of regions 102 defined thereon. Then different semiconductor processes are performed to the wafer 100, and the required semiconductor devices are formed in each region 102. The regions are separated to form chips possessing a specific function. As shown in the right of FIG. 1, when a region 102 is predetermined to be a dynamic random access memory (DRAM) chip, memory core array is formed in a center region of each region 102, and a sub-region 104 with a high device integration density is obtained. In the meantime, a peripheral circuit or I/O pads are formed in a peripheral region of each region 102, and a sub-region 106 with a low device integration density is obtained. Therefore each region 102 includes both of the sub-region 104 of high integration density and the sub-region 106 of low integration densities. When the regions 102 of different wafers 100 are predetermined to form chips possessing different specific function, such as analog chip, flash memory chip, or CPU chip, the region 102 is formed to include many sub-regions 104/106 of high or low integration densities.
After separating the regions 102 to obtain the chips, the prior art is to stack and package the chips with different specific function, thus a semiconductor chip package 110 is obtained. As shown in FIG. 2, the conventional chip package 110 includes a carrier 112, a CPU chip 114a, a DRAM chip 114b, a flash memory chip 114c, and an analog chip 114d upwardly stacked on the carrier 112. And the active surfaces of each chip in the package 110 are electrically connected by TSV 116.
As mentioned above, the conventional chips respectively possess one specific function, and each chip comprises kinds of semiconductor devices in the sub-regions with different integration densities. However, the devices are formed by the same processes. For example, to comply with the process requirement for fabricating the devices with high integration density, high-grade semiconductor processes are performed to the wafer even though the devices with low integration density need no such high-grade semiconductor processes. In fact, devices with different integration densities require processes of different grades. Therefore, wastes of cost and source have been caused when the semiconductor processes are performed to the wafer 100. Consequently, a semiconductor chip stack and manufacturing method that is able to improve process efficiency and to lower the cost is still in need.